System Partitioning for Multi-Chip Modules Under Timing and Capacity Constraints

ing step t o ensure timing correctness, followed b y packin and K&L algorithm t o satisfy capacity constraints w k l e minimizing net crossings. Our method is unique in that we minimize net crossin s while satisfying t tming and ca acity constraints. d s t results showed that our metho% eliminated timing violations and obtained com arable number of net crossings to that of FiducciaJMattheyses algorithm with similar run time. Our method can be extended t o use pa,rtitioning algorithms other than FiducciaEfMattheyses .